7.2 Latches and flip-flops

A flip-flop is a memory element with two stable states. It may have several inputs, and it has two outputs, \(Q\) and \(\overline{Q}\), as shown in Figure 7.1. The output \(Q\) defines the state of the flip-flop: when \(Q=1\) the flip-flop is in the SET state, and when \(Q=0\) it is in the RESET state. The second output \(\overline{Q}\) is always the complement of \(Q\), so that when \(Q\) is at logic 1, \(\overline{Q}\) is at logic 0, and vice versa. A flip-flop can therefore store exactly one bit of information.

In a synchronous sequential circuit the memory elements are clocked flip-flops, which are generally edge-triggered. In an asynchronous sequential circuit the memory elements are unclocked flip-flops (latches) or time-delay elements, which are generally level-triggered. Because it has two stable states (the 1 state and the 0 state), a flip-flop circuit is also known as a bistable multivibrator.

The essential difference between a latch and a flip-flop lies in when the stored content may change. The output of a latch is continuously affected by its inputs for as long as the enable signal is asserted: while the latch is enabled, its content changes as soon as its inputs change. The content of a flip-flop, on the other hand, can change only at the rising or the falling edge of the enable signal, which is usually the controlling clock. Once that edge has passed, the content of the flip-flop remains constant even if the inputs change. There are four main types of latch and flip-flop, namely SR, D, JK and T. They differ in the number of inputs they have and in the way they change state, and each type exists in several variations that improve its operation.

(a) The SR latch with NOR gates

An SR (set–reset) latch has two inputs, set (\(S\)) and reset (\(R\)), and two outputs \(Q\) and \(\overline{Q}\), which are complements of each other: if one output is 0 the other must be 1. The latch can be built from NOR gates or from NAND gates.

With NOR gates the latch is obtained by connecting two gates back to back, as in Figure 7.2. The cross-coupled connection from the output of each gate to an input of the other constitutes a feedback path. The circuit is not clocked and is therefore classified as an asynchronous sequential circuit. Its block symbol is shown in Figure 7.3.

We denote the present state by \(Q_n\) and the next state, after the inputs have acted, by \(Q_{n+1}\). Recalling that the output of a NOR gate is 1 only when both of its inputs are 0, we can examine the four input combinations in turn. For \(S=0\) and \(R=0\) each gate simply inverts the output of the other, so the latch remains in its present state: \(Q_{n+1}=Q_n\), which is the no-change condition. For \(S=0\) and \(R=1\) the gate driven by \(R\) is forced to give \(Q=0\), whatever the previous state; the latch is reset, \(Q_{n+1}=0\). For \(S=1\) and \(R=0\) the gate driven by \(S\) is forced to give \(\overline{Q}=0\), and hence \(Q=1\); the latch is set, \(Q_{n+1}=1\), whether \(Q_n\) was 0 or 1. Finally, for \(S=1\) and \(R=1\) both outputs are forced to 0, which violates the requirement that the two outputs be complements of each other. Since this condition contradicts the basic definition of a flip-flop, it is called the undefined (invalid) condition and must not be used. These results form the truth table of the NOR latch.

Figure 7.4 shows a typical set of input waveforms and the resulting output. A pulse on \(S\) sets \(Q\) to 1, and \(Q\) stays at 1 after the pulse has gone; a later pulse on \(R\) resets \(Q\) to 0, and further pulses on \(R\) leave it at 0 until \(S\) is pulsed again. The behaviour is summarised in the compact table that follows.

(b) The SR latch with NAND gates

The latch may equally be built from two cross-coupled NAND gates (Figures 7.5 and 7.6). The output of a NAND gate is 0 only when both its inputs are 1, so a 0 on either input forces that gate’s output to 1. The inputs of the NAND latch are therefore active low: the latch responds to a 0, not to a 1.

Taking the input combinations in turn, \(S=0\) and \(R=0\) force both outputs to 1, which again violates the complementary relation between \(Q\) and \(\overline{Q}\); this is the undefined condition of the NAND latch. With \(S=0\) and \(R=1\) the latch is set, \(Q_{n+1}=1\), whether \(Q_n\) was 0 or 1. With \(S=1\) and \(R=0\) it is reset, \(Q_{n+1}=0\). With \(S=1\) and \(R=1\) each gate inverts the output of the other and the latch remains in its present state, \(Q_{n+1}=Q_n\). The truth table is thus the NOR-latch table with every input complemented.

Exam tip. The forbidden input of the NOR latch is \(S=R=1\); that of the NAND latch is \(S=R=0\). The NOR latch holds its state for \(S=R=0\), the NAND latch for \(S=R=1\).

(c) The gated SR latch

A gated SR latch can change its output state only when an enabling signal is present together with the required inputs. When the latch is not enabled, its output does not change, whatever inputs are applied. In other words, the latch is active while the ENABLE signal (EN) is HIGH and inactive while it is LOW. Figure 7.7 shows the circuit: two NAND steering gates, each fed by EN and by one of the inputs, drive a NAND latch.

When \(\text{EN}=0\) both steering gates give 1, which is the hold condition of the NAND latch, so \(Q\) cannot change. When \(\text{EN}=1\) each steering gate inverts its data input and passes \(\overline{S}\) and \(\overline{R}\) to the active-low latch. The steering gates thus convert the active-low NAND latch into an active-high one, which behaves exactly like the NOR latch while it is enabled.

Figure 7.8 illustrates the operation. During the first enable pulse \(S=0\) and \(R=1\), so \(Q\) is reset to 0; during the second \(S=1\) and \(R=0\), so \(Q\) is set to 1, and it remains at 1 while EN is low even though \(S\) and \(R\) change. During the third enable pulse \(S=0\), \(R=1\) and \(Q\) returns to 0, and during the fourth \(Q\) is set once more.

(d) Edge triggering and the clocked SR flip-flop

A flip-flop that responds only at a transition of the clock is said to be edge-triggered. In positive-edge triggering the flip-flop acts at the transition of the clock from 0 to 1, and in negative-edge triggering at the transition from 1 to 0; in each case the transition point is the only instant at which the inputs are sampled (Figure 7.9). On a circuit symbol the clock input is marked with a small triangle (the dynamic indicator); a bubble in front of the triangle denotes negative-edge triggering (Figure 7.10).

If the \(S\) and \(R\) inputs control the outputs only when a clock transition occurs, the circuit is called a clocked SR flip-flop. Since the clock signal synchronises its operation, the clocked SR flip-flop is also known as a synchronous SR flip-flop. Its symbols are shown in Figure 7.10, and a NAND realisation, in which the steering gates are opened by a narrow pulse derived from the clock edge, in Figure 7.11. At each active edge the flip-flop obeys the truth table of the gated latch; between edges it holds its state.

Example 7.1. Draw the output waveform of a positive-edge-triggered SR flip-flop for the clock, \(S\) and \(R\) inputs shown in Figure 7.12. Take \(Q=1\) initially.

Solution. The flip-flop looks at \(S\) and \(R\) only at the rising edges of the clock, and an input that changes just after an edge is read at its old value. Reading the inputs at each rising edge, we obtain the following table.

Hence \(Q\) stays high until edge 2, is low from edge 2 to edge 3, high from edge 3 to edge 5, low from edge 5 to edge 6 and high thereafter, as drawn in the bottom trace of Figure 7.12. The changes of \(S\) and \(R\) between edges have no effect on \(Q\).

Example 7.2. The waveforms of Figure 7.13 are applied to the positive-edge-triggered SR flip-flop of Figure 7.14, initially reset. Draw the output \(Q\).

Solution. Again only the levels at the rising edges matter. At edge 1, \(S=0\) and \(Q\) is either held at 0 or reset to 0; in either case \(Q=0\). At edge 2, \(S=0\) and \(R=1\) (both inputs change just after this edge), so \(Q\) remains reset. At edge 3, \(S=1\) and \(R=0\), so \(Q\) is set to 1. At edge 4, \(S=0\) and \(R=1\), and \(Q\) is reset to 0. At edges 5 and 6, \(S=1\) and \(R=0\), so \(Q\) is set at edge 5 and remains 1. The output is therefore 0 up to edge 3, 1 between edges 3 and 4, 0 between edges 4 and 5, and 1 from edge 5 onwards.

Example 7.3. The waveforms \(S\) and \(R\) of Figure 7.16 are applied to the NOR latch of Figure 7.15. Draw the output \(Q\), taking \(Q=0\) initially.

Solution. A latch has no clock, so \(Q\) responds at the moment an input becomes active. At \(t_1\) the pulse on \(S\) sets \(Q=1\). At \(t_2\) the pulse on \(R\) resets \(Q=0\). At \(t_3\) \(S\) sets \(Q=1\) again, and at \(t_4\) \(R\) resets it to 0. The pulse on \(R\) at \(t_5\) finds the latch already reset and changes nothing. At \(t_6\) \(S\) sets \(Q=1\), and the second \(S\) pulse at \(t_7\) leaves it at 1. Between pulses \(S=R=0\) and the latch holds its state, which gives the output trace of Figure 7.16.

(e) The D flip-flop

In the SR bistable the undefined input condition must always be avoided. A simple way of guaranteeing this is to connect an inverter between the set and reset inputs, so that a single data input \(D\) drives \(S\) directly and \(R\) through the inverter. The result is the D flip-flop, also called the delay flip-flop or D-type bistable (Figure 7.17). Since \(S=D\) and \(R=\overline{D}\), the two inputs can never be equal, and the forbidden condition cannot occur. The D flip-flop is the most widely used of all the clocked flip-flop types. A gate-level realisation is shown in Figure 7.18.

At the active edge the D flip-flop is set if \(D=1\) and reset if \(D=0\); in either case the output takes the value that \(D\) had at the edge, and it holds that value until the next edge. The table below is written for a negative-edge-triggered device.

(f) The JK flip-flop

A JK flip-flop has characteristics very similar to those of the SR flip-flop; the only difference is that the input condition that is undefined for the SR flip-flop, \(S=R=1\), is given a useful meaning. The inputs \(J\) and \(K\) act like \(S\) and \(R\) to set and reset the flip-flop respectively. When \(J=K=1\) the flip-flop is in the toggle state: its output switches to the complementary state every time a clock pulse arrives. The symbol is shown in Figure 7.19 and a NAND realisation in Figure 7.20. In that circuit the output \(\overline{Q}\) is fed back to the steering gate that receives \(J\), and \(Q\) to the gate that receives \(K\). A set command can therefore reach the latch only when \(Q=0\) and a reset command only when \(Q=1\), so that for \(J=K=1\) exactly one steering gate is open and the flip-flop changes state.

(g) The race-around condition and the master–slave JK flip-flop

The feedback that makes the JK flip-flop toggle also creates a difficulty when the circuit of Figure 7.20 is level-triggered, that is, when the steering gates are open for the whole time that the clock is high. Suppose that \(J=K=1\) and that the clock goes high. After one propagation delay \(\Delta t\) of the gates the output toggles. The new values of \(Q\) and \(\overline{Q}\) are fed back to the steering gates, which are still open, so after a further interval \(\Delta t\) the output toggles again, and it continues to toggle in this way for as long as the clock remains high (Figure 7.21). When the clock finally returns to 0 the output is left in a state that depends on the ratio of the pulse width to \(\Delta t\), and so is unpredictable. This repeated toggling during a single clock pulse is called the race-around condition.

If the clock pulse width \(t_p\), the propagation delay \(\Delta t\) and the clock period \(T\) satisfy

\[t_p<\Delta t<T,\]

the output has no time to toggle a second time before the steering gates close, and race-around cannot occur. Clock pulses as narrow as this are hard to produce reliably, and in practice the problem is avoided either by edge triggering, in which the inputs are sampled only during an extremely short interval at the clock transition, or by the master–slave construction.

The master–slave JK flip-flop consists of two gated SR latches in cascade (Figure 7.22). The first, the master, receives \(J\) and \(K\) and is enabled by the clock; the second, the slave, takes its inputs from the outputs of the master and is enabled by the complemented clock \(\overline{\text{Clk}}\). The outputs \(Q\) and \(\overline{Q}\) of the slave are the outputs of the flip-flop, and they are fed back to the steering gates of the master. While the clock is high the master responds to \(J\) and \(K\), but the slave is disabled and the output cannot change, so there is no closed path through which the output could race. When the clock falls the master is disabled and frozen, and the slave is enabled and copies the state of the master to the output. The feedback signals therefore change only after the master has been isolated from its inputs.

The output of a master–slave flip-flop changes once per clock cycle, at the falling edge of the clock, and for \(J=K=1\) it toggles exactly once per clock pulse whatever the pulse width. The truth table is that of the JK flip-flop, with the change of state occurring at the trailing edge of the clock pulse.

Exam tip. Race-around occurs only in a level-triggered JK flip-flop with \(J=K=1\) and \(t_p>\Delta t\). It is eliminated by the master–slave arrangement or by edge triggering.

(h) The T flip-flop

If the two inputs \(J\) and \(K\) of a JK flip-flop are tied together, the result is the T flip-flop, with a single input \(T\) and the two outputs \(Q\) and \(\overline{Q}\) (Figure 7.23). The name indicates its ability to toggle. With \(J=K=T\), the JK table shows that the flip-flop has only two modes, the memory state (\(T=0\)) and the toggle state (\(T=1\)). Because of this, the T flip-flop is the natural choice for counters and for any sequential circuit in which an operation has to be switched alternately on and off. A gate-level realisation is shown in Figure 7.24.

(i) Characteristic equations

The characteristic equation of a flip-flop expresses the next state \(Q_{n+1}\) as a Boolean function of the inputs and the present state \(Q_n\). It is obtained by entering \(Q_{n+1}\) from the truth table into a Karnaugh map and minimising.

For the SR flip-flop, the map of \(Q_{n+1}\) in the variables \(S\), \(R\) and \(Q_n\) (Figure 7.25) has 1s at \(SRQ_n=001,\,100,\,101\) and don’t-cares at \(110\) and \(111\), the invalid inputs. Grouping the row \(S=1\) (with the don’t-cares) and the pair \(\overline{S}\,\overline{R}Q_n,\;S\overline{R}Q_n\), we obtain

\[\boxed{Q_{n+1}=S+\overline{R}\,Q_n},\qquad SR=0 .\]

For the JK flip-flop the map (Figure 7.26) has 1s at \(JKQ_n=001,\,100,\,101,\,110\). The pair \(001,\,101\) gives \(\overline{K}Q_n\), and the pair \(100,\,110\) gives \(J\overline{Q}_n\), so that

\[\boxed{Q_{n+1}=J\,\overline{Q}_n+\overline{K}\,Q_n}.\]

For the T flip-flop, setting \(J=K=T\) in the JK equation, or reading the map of Figure 7.27, gives

\[\boxed{Q_{n+1}=T\,\overline{Q}_n+\overline{T}\,Q_n=T\oplus Q_n}.\]

For the D flip-flop the map of Figure 7.28 has 1s in the whole row \(D=1\), so

\[\boxed{Q_{n+1}=D}.\]

The output therefore reproduces the input one clock period later, which is the origin of the name delay flip-flop.

(j) Excitation tables

In design problems we know the transition \(Q_n\to Q_{n+1}\) that a flip-flop must make, and we need the inputs that produce it. A table listing these inputs is called an excitation table; it is the truth table read backwards. For the JK flip-flop, the transition \(0\to0\) is produced either by \(J=0,K=0\) (no change) or by \(J=0,K=1\) (reset), so it requires \(J=0\) with \(K\) arbitrary. The transition \(1\to0\) is produced by \(J=0,K=1\) or by \(J=1,K=1\), so it requires \(K=1\) with \(J\) arbitrary. The transition \(1\to1\) requires \(K=0\) with \(J\) arbitrary, and \(0\to1\) requires \(J=1\) with \(K\) arbitrary. These four cases are summarised in Figure 7.29. Reasoning in the same way for the other flip-flops gives the combined excitation table below, in which x denotes a don’t-care.