Theory, worked examples and 20 previous-year questions with full solutions — IIT-JAM, GATE, JEST and CSIR NET-JRF, 2020 onwards.
Theory
The p–n junction diode of the previous chapters is a two-terminal device whose current is controlled only by the voltage across it. When a second junction is placed close behind the first, so that the carriers injected by one junction are collected by the other, we obtain a three-terminal device in which a small current at one terminal controls a much larger current between the other two. This device, the bipolar junction transistor, is the basis of the amplifier. In this chapter we describe its construction and mode of operation, define its three basic configurations together with their characteristics and current gains, and then develop the d.c. biasing of the common-emitter transistor: the choice of operating point, the fixed-bias, emitter-stabilised, voltage-divider and voltage-feedback circuits, and the thermal stability of the operating point.
4.1 Construction and operation of the transistor
(a) Construction
A transistor is made by placing a layer of semiconductor between two layers of the opposite type. If a thin layer of n-type material is sandwiched between two layers of p-type material, the result is a pnp transistor; if a thin p-type layer is sandwiched between two n-type layers, the result is an npn transistor. The transistor is therefore a three-layer semiconductor device consisting either of two n-type layers and one p-type layer, or of two p-type layers and one n-type layer. Both types are shown with their proper d.c. biasing in Figure 4.1.
Figure 4.1 The two types of transistor, with their biasing supplies: (a) pnp, (b) npn.
The three layers are not alike. The emitter layer is heavily doped, the base is lightly doped and the collector is only lightly doped. The outer layers are much wider than the sandwiched p- or n-type layer; a typical ratio of the total width to the width of the centre layer is 150 : 1. The doping of the sandwiched layer is also considerably less than that of the outer layers, typically in the ratio 1 : 10 or less. This low doping level limits the number of free carriers in the base, and so decreases its conductivity, or equivalently increases its resistance.
The terminals are labelled \(E\) for emitter, \(C\) for collector and \(B\) for base. The name bipolar junction transistor (BJT) reflects the fact that both holes and electrons take part in the injection process into the oppositely doped material, in contrast to unipolar devices in which only one type of carrier is involved.
(b) Transistor action
We describe the basic operation with the pnp transistor of Figure 4.1(a); the operation of the npn transistor is exactly the same once the roles of electrons and holes are interchanged. Consider first the transistor with the base–collector bias removed, as in Figure 4.2. The emitter–base junction is then simply a forward-biased p–n junction. The applied bias reduces the width of its depletion region, and there is a heavy flow of majority carriers from the p-type emitter into the n-type base.
Figure 4.2 The forward-biased emitter–base junction of a pnp transistor.
Now remove instead the base–emitter bias, leaving only the collector supply, as in Figure 4.3. The collector–base junction is then a reverse-biased p–n junction. As we know from the diode, the flow of majority carriers across a reverse-biased junction is zero, and only a small flow of minority carriers remains. Normal operation of the transistor combines these two situations: one p–n junction of the transistor is forward-biased, while the other is reverse-biased.
Figure 4.3 The reverse-biased collector–base junction of a pnp transistor.
In Figure 4.4 both biasing potentials have been applied to the pnp transistor, and the resulting majority- and minority-carrier flows are indicated. The widths of the two depletion regions show clearly which junction is forward-biased (the narrow one) and which is reverse-biased (the wide one). A large number of majority carriers (holes) diffuse across the forward-biased p–n junction into the n-type base. Because the base is very thin and has a low conductivity, only a very small fraction of these carriers follow the high-resistance path to the base terminal; this small fraction constitutes the base current. The great majority of the injected holes diffuse across the base to the reverse-biased junction and are swept into the p-type material connected to the collector terminal. The reason is that the holes injected into the n-type base are minority carriers there, and all minority carriers that reach the depletion region of a reverse-biased junction are carried across it, exactly as in the reverse-biased diode. This injection of minority carriers into the base and their collection by the reverse-biased junction account for the flows indicated in Figure 4.4.
Figure 4.4 Majority- and minority-carrier flows in a pnp transistor.
(c) The current relations
If we apply Kirchhoff’s current law to the transistor of Figure 4.4, treating it as a single node, the emitter current must equal the sum of the collector and base currents:
\[\boxed{I_E=I_C+I_B}.\]
The collector current itself has two components. The first is the majority-carrier component, the holes injected by the emitter and collected across the reverse-biased junction. The second is the minority-carrier component, which flows across the reverse-biased collector–base junction even when no carriers are injected; it is called the leakage current and is denoted \(I_{CO}\), the collector current with the emitter terminal open. Hence
The common-base configuration for pnp and npn transistors is shown in Figures 4.5 and 4.6. The name comes from the fact that the base is common to both the input (emitter) side and the output (collector) side of the configuration, and is usually the terminal closest to ground potential. All current directions are taken as the actual directions of conventional current: in the pnp transistor the emitter current enters at the emitter and the collector and base currents leave, while in the npn transistor every direction is reversed. In each case the arrow in the circuit symbol is on the emitter and points in the direction of conventional emitter current.
Figure 4.5 Notation and symbols used with the common-base configuration: pnp transistor.Figure 4.6 Notation and symbols used with the common-base configuration: npn transistor.
To describe completely the behaviour of a three-terminal device such as the common-base amplifier, two sets of characteristics are needed: one for the driving-point, or input, parameters and one for the output side.
(b) Input characteristics of the common-base configuration
The input set for the common-base amplifier, shown in Figure 4.7 for an npn silicon transistor, relates the input current \(I_E\) to the input voltage \(V_{BE}\) for various levels of the output voltage \(V_{CB}\). The curves resemble the forward characteristic of a silicon diode: very little emitter current flows until \(V_{BE}\) reaches about 0.6–0.7 V, after which the current rises steeply. Increasing the collector–base voltage has only a small effect, slightly steepening the curves at higher currents.
Figure 4.7 Input, or driving-point, characteristics of a common-base silicon transistor.
(c) Output characteristics of the common-base configuration
The output set relates the output current \(I_C\) to the output voltage \(V_{CB}\) for various levels of the input current \(I_E\), as in Figure 4.8. These characteristics have three basic regions of interest: the active, cut-off and saturation regions. The active region is the one normally employed for linear (undistorted) amplifiers. In the active region the collector–base junction is reverse-biased, while the base–emitter junction is forward-biased.
Figure 4.8 Output, or collector, characteristics of a common-base transistor amplifier.
At the lower end of the active region the emitter current is zero, and the collector current is then simply the reverse saturation current \(I_{CO}\). The circuit condition that exists when \(I_E=0\) is shown in Figure 4.9. This current is often written \(I_{CBO}\), the collector-to-base current with the emitter open, and so \(I_{CBO}=I_{CO}\). Its magnitude is very small (microamperes for germanium, nanoamperes for silicon) and so small that the line \(I_E=0\) almost coincides with the \(V_{CB}\) axis in Figure 4.8. It is, however, strongly dependent on temperature and increases rapidly as the temperature rises.
Figure 4.9 The reverse saturation current \(I_{CBO}=I_{CO}\) with the emitter open.
As the emitter current increases above zero, the collector current increases to a magnitude essentially equal to that of the emitter current, as required by the basic current relations of Section 4.1. Note also the almost negligible effect of \(V_{CB}\) on the collector current in the active region: the curves are nearly horizontal. The remaining two regions are defined by the bias of the junctions. In the cut-off region the collector–base and base–emitter junctions are both reverse-biased. In the saturation region the collector–base and base–emitter junctions are both forward-biased. The saturation region lies to the left of \(V_{CB}=0\), where the collector current falls rapidly towards zero.
(d) The common-base current gain \(\alpha\)
In the d.c. mode the levels of \(I_C\) and \(I_E\) due to the majority carriers are related by a quantity called alpha, defined by
\[\boxed{\alpha_{dc}=\frac{I_C}{I_E}},\]
where \(I_C\) and \(I_E\) are the levels of current at the operating point. Since the collector current consists of the majority component \(\alpha I_E\) together with the leakage current, the collector current of Section 4.1 may be written
For a.c. situations, in which the operating point moves along the characteristic curves, an a.c. alpha is defined as the ratio of a small change in collector current to the corresponding change in emitter current, with the collector–base voltage held constant:
The a.c. alpha is formally called the common-base short-circuit amplification factor. Since \(I_C<I_E\), the current amplification \(I_C/I_E\) of the common-base configuration is always less than 1, typically 0.90 to 0.998. Nevertheless the configuration can amplify voltage, because a small input voltage across the low resistance of the forward-biased emitter junction produces a nearly equal current in the high-resistance output circuit; typical values of the voltage amplification \(V_o/V_i\) for the common-base configuration lie between 50 and 300.
(e) The common-emitter configuration
The common-emitter configuration for npn and pnp transistors is shown in Figure 4.10. It takes its name from the fact that the emitter is common to both the input (base) and output (collector) terminals. The current directions are again the actual directions of conventional current, so that for both types the relation \(I_E=I_C+I_B\) still holds.
Figure 4.10 Notation and symbols used with the common-emitter configuration: (a) npn transistor, (b) pnp transistor.
Two sets of characteristics are again needed to describe fully the behaviour of the common-emitter amplifier: one for the input, or base–emitter, circuit and one for the output, or collector–emitter, circuit. The output characteristics relate the output current \(I_C\) to the output voltage \(V_{CE}\) for various levels of the input current \(I_B\). The input characteristics relate the input current \(I_B\) to the input voltage \(V_{BE}\) for various levels of the output voltage \(V_{CE}\). Both sets are shown in Figure 4.11 for a silicon transistor. The three regions are defined exactly as for the common-base configuration. In the active region the collector–base junction is reverse-biased, while the base–emitter junction is forward-biased. In the cut-off region the collector–base and base–emitter junctions are both reverse-biased. In the saturation region the collector–base and base–emitter junctions are both forward-biased.
Figure 4.11 Characteristics of a silicon transistor in the common-emitter configuration: (a) collector characteristics, (b) base characteristics.
In the collector characteristics the base current is measured in microamperes while the collector current is in milliamperes, which already shows the large current gain of this configuration. The active region lies to the right of the vertical dashed line at \(V_{CE_{\text{sat}}}\) and above the curve \(I_B=0\); the saturation region is the narrow strip to the left of \(V_{CE_{\text{sat}}}\), and the region below \(I_B=0\) is the cut-off region. The base characteristics resemble those of a forward-biased silicon diode, with a turn-on voltage of about 0.7 V, and shift only slightly to the right as \(V_{CE}\) increases.
(f) Leakage current and the common-emitter current gain \(\beta\)
We can now relate the collector current to the base current. Starting from \(I_C=\alpha I_E+I_{CBO}\) and substituting \(I_E=I_C+I_B\),
The current \(I_{CEO}\) is the collector current that flows when the base is open (\(I_B=0\)), and the corresponding circuit condition is shown in Figure 4.12. Since \(1+\beta=1+\alpha/(1-\alpha)=1/(1-\alpha)\), it may also be written
\[\boxed{I_{CEO}=(1+\beta)I_{CBO}},\]
so that the leakage current of the common-emitter configuration is larger than that of the common-base configuration by the large factor \(1+\beta\). This is why the curve \(I_B=0\) in Figure 4.11(a) lies visibly above the \(V_{CE}\) axis.
Figure 4.12 The circuit condition related to \(I_{CEO}\): the base is open, \(I_B=0\).
In the d.c. mode the levels of \(I_C\) and \(I_B\) are related by a quantity called beta, defined by
\[\boxed{\beta_{dc}=\frac{I_C}{I_B}},\]
where \(I_C\) and \(I_B\) are the levels of current at the operating point. For a.c. situations, in which the operating point moves along the characteristic curves, an a.c. beta is defined by
The formal name for \(\beta_{ac}\) is the common-emitter forward-current amplification factor. Typical values of \(\beta\) range from about 50 to more than 400, and the two relations \(\beta=\alpha/(1-\alpha)\) and, inversely, \(\alpha=\beta/(1+\beta)\) allow either gain to be found from the other.
Exam tip. Remember \(\beta=\dfrac{\alpha}{1-\alpha}\), \(\alpha=\dfrac{\beta}{1+\beta}\), \(1+\beta=\dfrac{1}{1-\alpha}\) and \(I_{CEO}=(1+\beta)I_{CBO}\). For example, \(\alpha=0.99\) gives \(\beta=99\), and \(\alpha=0.98\) gives \(\beta=49\): a small change in \(\alpha\) produces a large change in \(\beta\).
(g) The common-collector configuration
The third and final transistor configuration is the common-collector configuration, shown in Figure 4.13 with the proper current directions and voltage notation. The common-collector configuration is used mainly for impedance matching, since it has a high input impedance and a low output impedance, the opposite of the common-base and common-emitter configurations.
Figure 4.13 Notation and symbols used with the common-collector configuration: (a) pnp transistor, (b) npn transistor.
A common-collector circuit is shown in Figure 4.14, with the load resistor connected from the emitter to ground. Note that the collector is tied to ground even though the transistor is connected in a manner similar to the common-emitter configuration. Since \(I_E\approx I_C\) and the input current is again \(I_B\), for all practical purposes the output characteristics of the common-collector configuration are the same as those of the common-emitter configuration, with \(I_C\) replaced by \(I_E\) and \(V_{CE}\) by \(V_{EC}\).
Figure 4.14 The common-collector configuration, with the load resistor \(R\) from emitter to ground.
4.3 D.C. biasing of the common-emitter transistor
(a) Introduction
The analysis or design of a transistor amplifier requires a knowledge of both its d.c. and its a.c. response. The increased a.c. power at the output is the result of a transfer of energy from the applied d.c. supplies, so the analysis or design of any electronic amplifier has two components: the d.c. portion and the a.c. portion. Fortunately, the superposition theorem applies, and the investigation of the d.c. conditions can be separated completely from the a.c. response. We must nevertheless bear in mind that, at the design stage, the choice of parameters for the required d.c. levels will affect the a.c. response, and vice versa.
The d.c. level of operation of a transistor is controlled by several factors, including the range of possible operating points on the device characteristics. Each design also determines the stability of the system, that is, how sensitive it is to variations of temperature. Although a number of networks will be analysed, there is an underlying similarity between the analyses because of the repeated use of the following basic relations for a transistor in the active region:
Since the operating point is a fixed point on the characteristics, it is also called the quiescent point, abbreviated Q-point; quiescent means quiet, still, inactive. Figure 4.15 shows a general output characteristic of a device with four operating points, \(A\), \(B\), \(C\) and \(D\), indicated. The biasing circuit can be designed to set the device operation at any of these points, or at others within the active region. The maximum ratings are indicated on the characteristics by a horizontal line at the maximum collector current \(I_{C_{\max}}\) and a vertical line at the maximum collector-to-emitter voltage \(V_{CE_{\max}}\). The maximum power constraint is defined by the curve \(P_{C_{\max}}\) in the same figure; along this curve \(I_CV_{CE}=P_{C_{\max}}\), so it is a hyperbola. At the lower end of the scales lie the cut-off region, defined by \(I_B\le0\ \mu\text{A}\), and the saturation region, defined by \(V_{CE}\le V_{CE_{\text{sat}}}\).
Figure 4.15 Various operating points within the limits of operation of a transistor.
If no bias were used, the device would initially be completely off, giving a Q-point at \(A\), namely zero current through the device and zero voltage across it. Since a device must be biased so that it can respond to the entire range of an input signal, point \(A\) would not be suitable.
For point \(B\), if a signal is applied to the circuit, the current and voltage of the device will vary about the operating point, allowing the device to respond to both the positive and the negative excursions of the input signal. If the input signal is properly chosen, the voltage and current of the device will vary, but not enough to drive the device into cut-off or saturation.
Point \(C\) would allow some positive and negative variation of the output signal, but the peak-to-peak value would be limited by the proximity of \(V_{CE}=0\ \text{V}\) and \(I_C=0\ \text{mA}\). Operating at point \(C\) also raises some concern about non-linearity, because the spacing between the \(I_B\) curves changes rapidly in this region. In general it is preferable to operate where the gain of the device is constant (linear), so that the amplification is the same over the entire swing of the input signal.
Point \(D\) sets the operating point of the device near the maximum voltage and power levels. The output voltage swing in the positive direction is thus limited if the maximum voltage is not to be exceeded.
Point \(B\) lies in a region of more linear spacing of the curves, and therefore appears to be the best operating point in terms of linear gain and the largest possible voltage and current swing. This is usually the desired condition for small-signal amplifiers, though not necessarily for power amplifiers. In this chapter we shall concentrate on biasing the transistor for small-signal amplification.
Having selected and biased the transistor at a desired operating point, we must also take into account the effect of temperature. Temperature causes device parameters such as the current gain \(\beta_{ac}\) and the leakage current \(I_{CEO}\) to change. Higher temperatures result in increased leakage currents in the device, which change the operating condition set by the biasing network. The network design must therefore also provide a degree of temperature stability, so that changes of temperature produce minimal changes in the operating point. This maintenance of the operating point can be specified by a stability factor\(S\), which indicates the degree of change in the operating point due to a variation of temperature. A highly stable circuit is desirable, and the stability of the basic bias circuits will be compared in Section 4.8.
(c) Regions of operation
For the transistor to be biased in its linear, or active, region of operation two conditions must hold. First, the base–emitter junction must be forward-biased (for an npn transistor, the p-region more positive), with a resulting forward-bias voltage of about 0.6 to 0.7 V. Secondly, the base–collector junction must be reverse-biased (the n-region more positive), with the reverse-bias voltage at any value within the maximum limits of the device. The states of the two junctions in the three regions of operation are summarised in the following table.
Region of operation
Base–emitter junction
Base–collector junction
Linear (active)
forward-biased
reverse-biased
Cut-off
reverse-biased
reverse-biased
Saturation
forward-biased
forward-biased
Exam tip. For an npn transistor a quick test of the region is: active if \(V_{BE}\approx0.7\) V and \(V_{CB}>0\) (that is, \(V_C>V_B\)); saturated if both junctions are forward-biased, so that \(V_{CE}\approx V_{CE_{\text{sat}}}\approx0.2\) V and \(I_C<\beta I_B\); cut off if \(V_{BE}\) is below the turn-on voltage, so that \(I_B\approx0\) and \(I_C\approx I_{CEO}\).
4.4 The fixed-bias circuit
The fixed-bias circuit of Figure 4.16 provides a relatively straightforward and simple introduction to transistor d.c. bias analysis. Although the network employs an npn transistor, the equations and calculations apply equally well to a pnp transistor configuration once all current directions and voltage polarities are reversed.
Figure 4.16 The fixed-bias circuit.
For the d.c. analysis the network can be isolated from the a.c. levels by replacing each capacitor with its open-circuit equivalent, since the reactance of a capacitor is infinite at zero frequency. In addition, the d.c. supply \(V_{CC}\) can be separated into two supplies, for analysis purposes only, as in Figure 4.17. This separates the input and output circuits, the only link between the two being the base current \(I_B\).
Figure 4.17 The d.c. equivalent of the fixed-bias circuit of Figure 4.16.
(a) The base–emitter loop
Consider first the base–emitter loop of Figure 4.18. Writing Kirchhoff’s voltage law clockwise around the loop, we obtain
\[-V_{CC}+I_BR_B+V_{BE}=0.\]
Note that the polarity of the voltage drop across \(R_B\) is fixed by the indicated direction of \(I_B\). Solving for the base current gives
\[\boxed{I_B=\frac{V_{CC}-V_{BE}}{R_B}}.\]
Figure 4.18 The base–emitter loop.
Since the supply voltage \(V_{CC}\) and the base–emitter voltage \(V_{BE}\) are constants, the choice of the base resistor \(R_B\) sets the level of base current at the operating point; the base current is “fixed” by \(R_B\), which gives the circuit its name.
(b) The collector–emitter loop
The collector–emitter section of the network appears in Figure 4.19, with the indicated direction of the current \(I_C\) and the resulting polarity across \(R_C\). In the active region the magnitude of the collector current is related directly to \(I_B\) through
\[I_C=\beta I_B.\]
Figure 4.19 The collector–emitter loop.
It is interesting to note that, since the base current is controlled by the level of \(R_B\) and \(I_C\) is related to \(I_B\) by the constant \(\beta\), the magnitude of \(I_C\) is not a function of the resistance \(R_C\). We may change \(R_C\) to any level without affecting \(I_B\) or \(I_C\), provided that the device remains in its active region. As we shall see, however, the level of \(R_C\) determines the magnitude of \(V_{CE}\), which is an important parameter. Applying Kirchhoff’s voltage law clockwise around the closed loop of Figure 4.19 gives
As a brief review of single- and double-subscript notation, recall that
\[V_{CE}=V_C-V_E,\]
where \(V_{CE}\) is the voltage from collector to emitter, and \(V_C\) and \(V_E\) are the voltages from collector and emitter to ground respectively. In the present circuit \(V_E=0\ \text{V}\), so that
\[V_{CE}=V_C.\]
In addition, since \(V_{BE}=V_B-V_E\) and \(V_E=0\ \text{V}\), we have \(V_{BE}=V_B\). Keep in mind that a voltage such as \(V_{CE}\) is measured by placing the positive lead of the voltmeter on the collector terminal and the negative lead on the emitter terminal, as in Figure 4.20, whereas \(V_C\) is the voltage from collector to ground and is measured as shown in the same figure. In this circuit the two readings are identical, but in the networks that follow they can be quite different.
Figure 4.20 Measuring \(V_{CE}\) and \(V_C\).
(c) Transistor saturation
The term saturation is applied to any system whose levels have reached their maximum values. For a transistor operating in the saturation region the current has its maximum value for the particular design; if the design is changed, the corresponding saturation level may rise or fall. Saturation is normally avoided in amplifiers, because the base–collector junction is then no longer reverse-biased and the amplified output signal would be distorted. An operating point in the saturation region is shown in Figure 4.21(a). It lies where the characteristic curves join, and the collector-to-emitter voltage is at or below \(V_{CE_{\text{sat}}}\); the collector current is also relatively high on the characteristics.
Figure 4.21 The saturation region: (a) actual, (b) approximate.
If we approximate the curves of Figure 4.21(a) by those of Figure 4.21(b), a quick and direct method of finding the saturation level becomes apparent. In Figure 4.21(b) the current is relatively high and the voltage \(V_{CE}\) is taken to be zero. Applying Ohm’s law, the resistance between the collector and emitter terminals is
The saturated transistor can therefore be replaced, for this purpose, by a short circuit between collector and emitter, as in Figure 4.22. To find the saturation current we set \(V_{CE}=0\ \text{V}\) and calculate \(I_{C_{\text{sat}}}\). For the fixed-bias configuration the short circuit has been applied in Figure 4.23, so that the voltage across \(R_C\) is the full supply voltage \(V_{CC}\). The resulting saturation current for the fixed-bias configuration is
Figure 4.22 Determining \(I_{C_{\text{sat}}}\): the collector–emitter path is replaced by a short circuit, \(R_{CE}=0\ \Omega\) (\(V_{CE}=0\) V, \(I_C=I_{C_{\text{sat}}}\)).Figure 4.23 Determining \(I_{C_{\text{sat}}}\) for the fixed-bias configuration.
(d) Load-line analysis
We now investigate how the network parameters define the possible range of Q-points and how the actual Q-point is determined. The network of Figure 4.24(a) establishes an output equation that relates the variables \(I_C\) and \(V_{CE}\),
\[V_{CE}=V_{CC}-I_CR_C,\]
while the output characteristics of the transistor, Figure 4.24(b), relate the same two variables. The Q-point must satisfy both relations at once, and is therefore found where the straight line defined by the network equation crosses the appropriate characteristic curve.
Figure 4.24 Load-line analysis: (a) the network, (b) the device characteristics.
To draw the straight line on the characteristics we need two points. If we choose \(I_C=0\ \text{mA}\), we are specifying the horizontal axis as the line on which one point lies; substituting \(I_C=0\) in the network equation gives
which defines one end of the line, as in Figure 4.25. If we now choose \(V_{CE}=0\ \text{V}\), which places the second point on the vertical axis, the network equation gives \(0=V_{CC}-I_CR_C\), and hence
as shown in Figure 4.25. This intercept is simply the saturation current found above.
Figure 4.25 The load line of the fixed-bias circuit.
By joining the two points defined by these equations, the straight line \(V_{CE}=V_{CC}-I_CR_C\) can be drawn. The resulting line in Figure 4.25 is called the load line, since it is defined by the load resistor \(R_C\). By solving for the resulting level of \(I_B\), the actual Q-point is established as the intersection of the load line with the characteristic curve for that base current.
If the level of \(I_B\) is changed by varying the value of \(R_B\), the Q-point moves up or down the load line, as shown in Figure 4.26.
Figure 4.26 Movement of the Q-point with increasing levels of \(I_B\).
It should be noted that, for a fixed \(R_B\), the Q-point moves towards the saturation region as the temperature of the device increases, as indicated in Figure 4.26. The reason is that
and both \(\beta\) and the reverse current \(I_{CBO}\), and hence \(I_{CEO}\), increase with temperature while \(I_B\) stays fixed.
If \(V_{CC}\) is held fixed and \(R_C\) is changed, the load line pivots about the point \(V_{CE}=V_{CC}\) on the horizontal axis, as shown in Figure 4.27; a larger \(R_C\) lowers the vertical intercept \(V_{CC}/R_C\). If \(I_B\) is held fixed, the Q-point moves along the curve \(I_{B_Q}\) as shown in the same figure, towards smaller \(V_{CE}\) as \(R_C\) increases.
Figure 4.27 The effect of increasing levels of \(R_C\) on the load line and the Q-point.
If \(R_C\) is fixed and \(V_{CC}\) is varied, the load line shifts parallel to itself, since its slope \(-1/R_C\) is unchanged, as shown in Figure 4.28. Lower values of \(V_{CC}\) move the line towards the origin, and with \(I_B\) fixed the Q-point moves to the left along the curve \(I_{B_Q}\).
Figure 4.28 The effect of lower values of \(V_{CC}\) on the load line and the Q-point.
Example 4.1. For the fixed-bias configuration shown below, with \(V_{CC}=+12\) V, \(R_B=240\,\text{k}\Omega\), \(R_C=2.2\,\text{k}\Omega\), coupling capacitors of \(10\,\mu\text{F}\) and \(\beta=50\), determine (a) \(I_{B_Q}\) and \(I_{C_Q}\); (b) \(V_{CE_Q}\); (c) \(V_B\) and \(V_C\); (d) \(V_{BC}\); (e) the saturation level.
Solution. (a) For d.c. the capacitors are open circuits, and the base–emitter loop gives
The load line therefore runs from \(V_{CE}=12\) V on the horizontal axis to \(I_C=5.45\) mA on the vertical axis. The quiescent current \(I_{C_Q}=2.35\) mA is far from the saturation level, at about one-half of the maximum value for this design, so the Q-point lies near the middle of the load line.
4.5 The emitter-stabilised bias circuit
The d.c. bias network of Figure 4.29 contains an emitter resistor, which improves the stability of the operating point over that of the fixed-bias configuration. The analysis is performed by first examining the base–emitter loop and then using the results to investigate the collector–emitter loop.
Figure 4.29 A BJT bias circuit with an emitter resistor.
(a) The base–emitter loop
The base–emitter loop of the network can be redrawn as in Figure 4.30. Writing Kirchhoff’s voltage law clockwise around this loop gives
\[-V_{CC}+I_BR_B+V_{BE}+I_ER_E=0.\]
Substituting \(I_E=(\beta+1)I_B\) and changing all signs,
Figure 4.30 The base–emitter loop of the emitter-stabilised circuit.
Note that the only difference between this equation for \(I_B\) and that obtained for the fixed-bias configuration is the term \((\beta+1)R_E\) in the denominator. An interesting result follows if this equation is used to sketch a series network that would lead to the same equation. Such a network is shown in Figure 4.31; solving it for the current \(I_B\) gives exactly the equation above. Apart from the base-to-emitter voltage \(V_{BE}\), the resistor \(R_E\) is reflected back into the input base circuit by the factor \((\beta+1)\). In other words, the emitter resistor, which is part of the collector–emitter loop, “appears as” \((\beta+1)R_E\) in the base–emitter loop. Since \(\beta\) is typically 50 or more, the emitter resistor appears much larger in the base circuit.
Figure 4.31 The series network that follows from the equation for \(I_B\).
In general, therefore, for the configuration of Figure 4.32, the resistance seen looking into the base is
\[\boxed{R_i=(\beta+1)R_E}.\]
Figure 4.32 The reflected impedance level of \(R_E\).
This result will prove useful in the analyses that follow, and it also provides an easy way of remembering the equation for \(I_B\). By Ohm’s law the current through a circuit is the net voltage divided by the resistance of the circuit. For the base–emitter circuit the net voltage is \(V_{CC}-V_{BE}\), and the resistance is \(R_B\) plus \(R_E\) reflected by the factor \((\beta+1)\).
(b) The collector–emitter loop
The collector–emitter loop is redrawn in Figure 4.33. Writing Kirchhoff’s voltage law clockwise around the indicated loop gives
\[I_ER_E+V_{CE}+I_CR_C-V_{CC}=0.\]
Substituting \(I_E\cong I_C\) and grouping terms,
\[\boxed{V_{CE}=V_{CC}-I_C(R_C+R_E)}.\]
Figure 4.33 The collector–emitter loop of the emitter-stabilised circuit.
The single-subscript voltage \(V_E\), the voltage from emitter to ground, is
\[V_E=I_ER_E,\]
while the voltage from collector to ground can be found from either
The collector saturation level, or maximum collector current, of the emitter-bias design can be found by the same approach as for the fixed-bias configuration: a short circuit is applied between collector and emitter, as in Figure 4.34, and the resulting current is
Figure 4.34 Determining \(I_{C_{\text{sat}}}\) for the emitter-stabilised bias circuit.
The addition of the emitter resistor reduces the collector saturation level below that of a fixed-bias configuration with the same collector resistor.
(d) Load-line analysis
The load-line analysis of the emitter-bias network differs only slightly from that of the fixed-bias configuration. The level of \(I_B\) found from the equation \(I_B=(V_{CC}-V_{BE})/[R_B+(\beta+1)R_E]\) defines the base-current curve on the characteristics of Figure 4.35, denoted \(I_{B_Q}\).
Figure 4.35 The load line for the emitter-bias configuration.
The collector–emitter loop equation that defines the load line is
as shown in Figure 4.35. The load line is therefore less steep than that of the fixed-bias circuit, its slope being \(-1/(R_C+R_E)\). Different levels of \(I_{B_Q}\) will, of course, move the Q-point up or down the load line.
Example 4.2. For the emitter-bias network shown below, with \(V_{CC}=+20\) V, \(R_B=430\,\text{k}\Omega\), \(R_C=2\,\text{k}\Omega\), \(R_E=1\,\text{k}\Omega\) (bypassed by \(40\,\mu\text{F}\)), coupling capacitors of \(10\,\mu\text{F}\) and \(\beta=50\), determine (a) \(I_B\); (b) \(I_C\); (c) \(V_{CE}\); (d) \(V_C\); (e) \(V_E\); (f) \(V_B\); (g) \(V_{BC}\); (h) \(I_{C_{\text{sat}}}\).
Solution. For d.c. all three capacitors are open circuits, so the bypass capacitor has no effect on the bias.
The load line thus joins \(V_{CE}=20\) V on the horizontal axis to \(I_C=6.67\) mA on the vertical axis, and the saturation current is a little more than three times the quiescent level \(I_{C_Q}=2.01\) mA.
4.6 Voltage-divider bias
In the bias configurations considered so far, the bias current \(I_{C_Q}\) and voltage \(V_{CE_Q}\) were functions of the current gain \(\beta\) of the transistor. However, \(\beta\) is sensitive to temperature, especially for silicon transistors, and its actual value is usually not well defined; it may differ widely even between transistors of the same type. It would therefore be desirable to develop a bias circuit that is less dependent on, or even independent of, the transistor beta. The voltage-divider bias configuration of Figure 4.36 is such a network. If it is analysed on an exact basis its sensitivity to changes in beta is found to be quite small, and if the circuit parameters are properly chosen the levels of \(I_{C_Q}\) and \(V_{CE_Q}\) can be almost totally independent of beta. There are two methods of analysis, the exact method and the approximate method.
Figure 4.36 The voltage-divider bias configuration.
(a) The exact method
For the d.c. analysis the input side of the network can be redrawn as in Figure 4.37. The Thévenin equivalent of the network to the left of the base terminal can then be found as follows.
Figure 4.37 The input side of the network of Figure 4.36 redrawn for d.c. analysis.
Thévenin resistance. The voltage source is replaced by a short-circuit equivalent, as in Figure 4.38. The resistors
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